1. Field of the Invention
This invention relates generally to a method and apparatus for writing circuit patterns using a laser system, and more particularly to a method and apparatus for writing circuit patterns using a quasi-continuous wave (cw) laser engine.
2. Description of Related Art
Multichip integrated circuit packages have been produced in the past by arranging a plurality of individual integrated circuit chips on a common substrate and then covering the chips on the substrate with a polymer film overlay layer or layers. The via holes are formed and metalized interconnections between the pads of the individual chips are provided. However, by itself, this packaging technique is highly dependent on the precise and accurate placement of the chips on the substrate. What is needed especially for automated packaging of integrated circuit chips, is a procedure which is less dependent on the highly accurate placement of the chips on the substrate.
A polymer film covers a plurality of integrated circuit chips adjacent to one another on an underlying substrate. The polymer film provides an insulative layer upon which a metalization pattern for interconnection of individual circuit chips is eventually deposited.
The chips include interconnection pads for connecting to other integrated circuit components or for connecting to other parts of the same chip. Via openings or apertures in the polymer dielectric layer are aligned with the interconnection pads. The pattern of interconnection conductor is disposed on the overlying polymer film so as to extend between at least some of the via openings so as to provide electrical connections between various parts of a chip or between several chips.
Metalization is preferably provided by sputtering a one thousand angstrom thick layer of titanium, followed by a one micron thick layer of copper over the polymer film and into the via holes. The metalization is preferably patterned by spraying or spinning a coating of photoresist on the copper surface, drying for about one half hour at approximately 90xc2x0 C. and exposing the positive resist material with a scanned ultraviolet (UV) laser beam under control of computerized artwork. A preferable photoresist material is Dynachem OFPR 800 photoresist.
To maximize the operating speed of the final system, interconnection from one chip to another is preferably accomplished with a minimum of capacitative loading and a minimum of interconnect length. Capacitative loading tends to slow down signal transmission such that high speeds attained on the chip cannot be maintained in communicating from one chip to another. Interconnection length between chips also contributes to propagation delay due to greater capacitative loading effects in the dielectric medium due to circuit length and also due to a self inductance of the interconnection circuit. The metalization is patterned to form very fine lines and spaces, typically under 1 mil in line width and 1 mil in line spacing.
The lithography system adapts to inaccurately placed chips by modifying database artwork patterns representing an ideal interconnect pattern so as to accommodate the actual position of integrated circuit chips. Commercially available chip placement devices are not sufficiently accurate to position chips with the resolution capability of a laser scan system.
Artwork is generated for the ideal positioning of integrated circuit chips using a computer-aided layout system. This computer-aided design system is provided with a first data base containing information as to the integrated circuit chips size, their ideal position and orientation if that is user specified, the location of connection pads on each integrated circuit chip and a list of the required connections among the various connection pads on the various integrated circuit chips. The computer-aided design system then provides a layout for the chips on the substrate and the printed circuit metalized conducting paths in the form of a second data base. The various conducting paths may preferably be stored in vector form as a series of straight line segments each specified by its starting and ending points. All interconnect, via hole definitions, and chip boundary definitions are stored in a file. The chip boundary definitions include an outline of a chip including its ideal position and orientation and an outline of the extent to which the chip can be misplaced. The actual positions and orientation of the integrated circuit components are determined from connection pad and chip outline information. Ideally, this process is performed automatically by using a charge-injection device (CID) camera and an image recognition technique to align each circuit chip and calculate offset and rotation information. In the process actually implemented and described hereinafter, the process is partly manual. More specifically, the substrate is aligned on the x-y table in both location and rotation according to fiducial marks on the substrate. The monitor for the CID camera is equipped with a bull""s-eye or cross-hair pattern on the center of the screen. When the fiducial mark on the substrate which corresponds to the mirror zero position is near the bull""s eye, the x and y position counters are reset to zero. The computer then supplies pulses to x and y stepping motors to step to the ideal position of the upper right hand pad of the integrated circuit chip. A mouse connected to the computer is used to move the image of one pad of the actual chip directly under the cross-hairs. The difference between the actual position and the ideal position is recorded. Then the computer steps the x-y table to the expected position of a pad on the opposite side of the integrated circuit chip, making the assumption that the chip is not rotated from the ideal position. The mouse is used again to position the image of the actual pad directly under the cross hairs. Again, the difference between the actual position and the ideal position is recorded. The offset and rotation of the actual chip is then recorded from the results of the two operations. The computer then goes to the next chip in sequence and determines its offset and rotation and this process is repeated until the offset and rotation of all the chips have been recorded. The information determined during this step is stored in a database which defines the chip positions. The ideal artwork is modified to match the actual chip position. All of the interconnect patterns and associated via holes are modified to incorporate the offset and rotation associated with each integrated circuit chip. The modified artwork is used to drive the adaptive lithography scanning system. The modified artwork is used to supply the commands for positioning the x-y table and to supply data to the high speed processor for driving the adaptive lithography scanning system and for modulating the laser beam so that a modified printed circuit pattern can be printed on the substrate.
The structure of the adaptive lithography system includes a primary laser beam path which starts from a quasi-cw laser system which is adjusted with optics to provide ultraviolet (UV) output. The laser provides a single beam which may be divided, with beam splitting optics, into as many beams as are required. The laser beam is then passed through an acousto-optical modulator which deflects the beam when a high frequency signal is applied. A plate with an aperture is positioned approximately one meter from the output of the modulator. The non-deflected beam is stopped by the plate and the deflected beam passes through the aperture.
The deflected beam is expanded to the desired diameter laser beam with a beam expander. The expanded beam is directed to a galvanometer driven scanner which has a (9-millimeter) diameter scanning mirror and an internal sensor which is coupled with a servo-amplifier to accurately position the mirror. The scanned beam is focused onto a substrate with a conventional plano-convex lens. A second laser is used to accurately determine the position of the scanning mirror at all times during the scan. The second laser beam is passed through a graticule and focused on a PIN diode detector.
A CID camera with a microscope objective is mounted to observe the area on the substrate where the laser beam focuses. Precise correlation between the laser beam position and the image of the CID camera is obtained. The substrate is positioned on a precision x-y table, which is positioned by precision screws attached to separate motors. The CID camera is connected to a video subsystem which drives a television display.
A microcomputer, such as a MS-DOS personal computer (PC), manages the process and dataflow. An input/output board connects special control electronics which manage the motion of the x-y table to the PC. The image data from the CID camera is sent through an interface board to a high speed processor which generates bit map patterns of the artwork stored in vector form. The control electronics for the adaptive lithography system can be divided into three major sections which are: x-y table control, mirror scan control, and laser data control. Circuitry is included which assures that the x-y table is in exact synchronism with the position of the scanning mirror. The lithography system operates by converting a file stored in rectangular vector form to a controlled flow of data which modulates a laser beam in synchronism with its position on the substrate to be exposed.
The system can be expanded to achieve higher throughput rates at a substantial savings by duplicating only essential parts of the device. The system can be duplicated as many times as required to obtain the desired throughput rate. The acousto-optic modulator, the expander, the scanner, and the focus lens as well as the alignment laser and the graticule must be duplicated. The x-y table, the CID camera, the PC, the laser and other equipment need not be duplicated.
There is a need for a lithography system and method for producing finer line widths. There is a further need for a lithography system and method for producing more precise integrated circuit interconnections.
Accordingly, an object of the present invention is to provide an improved lithography system and method.
These and other objects of the invention are achieved in a lithography system for providing interconnections of integrated circuits on a substrate. Included is a laser system with a high reflector and an output coupler that define an oscillator cavity. A gain medium and a mode locking device are positioned in the oscillator cavity. A diode pump source produces a pump beam that is incident on the gain medium. A processor is coupled to the laser system and stores a representation of interconnections for the integrated circuit. An output beam directing apparatus is coupled to the processor and directs the output beam to the substrate and form the interconnections.